Keeper-free volatile memory system

ABSTRACT

A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.

BACKGROUND

A memory bank is a unit of data storage in electronics, which is hardware-dependent. In a computer, for example, the memory bank may be determined by the physical organization of the hardware memory. In a typical static random-access memory (static RAM or SRAM), a bank may include multiple rows and columns of storage units, and is usually spread out across circuits. An SRAM is a type of semiconductor memory that uses bi-stable latching circuitry (e.g., a flip-flop or a portion thereof) to store each bit. In a single read or write operation, generally only one bank is accessed. Often a memory may be referred to as a register file.

A common feature of most modern memories is the use of a hierarchical bitline arrangement in which, instead of a single bitline that runs the complete height of a column of memory cells and connects to each cell in the column, a multi-level structure is used. Effectively, a single bitline is broken up into multiple “local bitlines”, each of which connects to the memory cells in a part of the column. A “global bitline” also runs the height of the column, and is connected to the local bitlines via switches. The memory read and write circuits connect to the global bitline, and not directly to the local bitline. During a memory access, only a local bitline in the relevant part of the column is connected (via its local-to-global switch) to the global bitline.

Often bit cell based register files are typically organized in multiple array banks. Each bank may be organized with multiple bit-cells on a local bitline. Wherein the bitline is local to the bank. Generally, a bitline conveys information when a memory access (e.g., read, write) occurs. Each bank may be connected to a dynamic global bitline that runs through or is included by each bank (hence, the global nature of the bit-line).

Generally, the global bitline is attached to two circuits. A keeper or pull-up device which serves the purpose of retaining the state of the global bitline when it is not actively driven. And a separate precharge device that pulls the global bitline “high” or up after the evaluation phase of the memory access completes.

Often the demands placed on the global bitline cause issues with the register file. For example, the keeper device is required to work across a wide range of process, voltage and temperature (PVT) variations, and prevent the global bitline from leaking current and transitioning to “low” when it is not desired. In another example, a contention may exist between the keeper device (pulling the global bitline “high”) and a bank’s bitline pull-down device (pulling the global bitline “low”).

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which that element is first introduced.

FIG. 1 depicts memory cells 100 in accordance with one embodiment.

FIG. 2 depicts a memory controller in accordance with one embodiment.

FIG. 3 depicts a memory cell in accordance with one embodiment.

FIG. 4 depicts a memory cell in accordance with another embodiment.

FIG. 5 depicts a conventional utilization of a global bitline (grblb) in a multi-banked memory.

FIG. 6 depicts read evaluation circuitry according to one embodiment.

FIG. 7 depicts a timing diagram for read evaluation 1 in one embodiment.

FIG. 8 depicts another timing diagram for read evaluation 0 in one embodiment.

FIG. 9 depicts a timing diagram in accordance with one embodiment.

FIG. 10 depicts a grblb precharge and keeper circuit in one embodiment.

FIG. 11 depicts output transistor bias circuitry according to one embodiment.

FIG. 12 depicts a timing diagram for read evaluation 1 in one embodiment.

FIG. 13 depicts current flow in one embodiment.

FIG. 14 depicts a timing diagram for read evaluation 0 in one embodiment.

FIG. 15 depicts current flow and voltages in one embodiment.

FIG. 16 depicts output transistor bias circuitry according to another embodiment.

FIG. 17 depicts output transistor bias circuitry according to yet another embodiment.

FIG. 18 depicts output transistor bias circuitry according to yet another embodiment.

FIG. 19 depicts a parallel processing unit 1920 in accordance with one embodiment.

FIG. 20 depicts a general processing cluster 2000 in accordance with one embodiment.

FIG. 21 depicts a memory partition unit 2100 in accordance with one embodiment.

FIG. 22 depicts a streaming multiprocessor 2200 in accordance with one embodiment.

FIG. 23 depicts a processing system 2300 in accordance with one embodiment.

FIG. 24 depicts an exemplary processing system 2400 in accordance with another embodiment.

FIG. 25 depicts a graphics processing pipeline 2500 in accordance with one embodiment.

FIG. 26 depicts a circuit system 2602 in accordance with one embodiment.

DETAILED DESCRIPTION

The following description describes embodiments of circuits in the context of machine memory devices, e.g., volatile single port or multi-port memory devices such as SRAMs (volatile static random access memory). The described circuit embodiments are however more generally applicable to signaling fanout scenarios where leakage becomes problematic.

The following description may be better understood with reference to the following terminology. Other terms should be accorded their conventional meaning in the art, or as indicated by context.

“Bit-storing cell” is another term for a memory cell, but also encompasses value-storing circuits such as latches and registers.

“Corresponding bit cell”, in the context of an output transistor, refers to the bit-storing cell that the output transistor interfaces to the global bitline.

“Distributed NOR gate” refers to NOR gate logic with inputs distributed across many circuits. In one embodiment a distributed NOR gate comprises inputs distributed across many different bit-storing cells of two or more memory banks.

“Drain” refers to the drain terminal of a transistor.

“Global bitline” refers to a bitline that spans groups of memory cells each with local bitlines.

“Global read evaluation signal” refers to a signal applied to multiple bit-storing cells simultaneously, one of which will actually be evaluated (using other signals) for its stored contents.

“Local bitlines” refers to bitlines that span only a sub-portion of the bit-storing cells that are spanned by a global bitline.

“Memory bank” refers to a group of bit-storing cells.

“Memory cell” refers to any circuit that stores a binary value.

“Memory controller” refers to logic that generates control signals for reading, writing, and managing memory cells.

“Output transistor” refers to a transistor that interfaces a memory cell to a global bitline.

“Pull-up transistor” refers to transistors between a given circuit node and a node at the voltage level of a power rail (“high binary voltage level”).

“Read signal” refers to signals from a memory controller to cause the stored bit value in a bit-storing cell to be output to a bitline.

“Shared inverter” refers to an inverter that interfaces a bias signal to multiple output transistors for different bit-storing cells.

“Source” refers to the source terminal on a transistor.

“Source bias” refers to a voltage level applied to a source terminal of a transistor. In particular, source bias refers to a non-VSS-level voltage applied to the source terminal.

“Stored bit value” refers to a binary “1” or “0” value stored in a bit-storing cell.

“Stored value” is a short reference for stored bit value.

Disclosed herein are embodiments of circuits that include a plurality of memory banks and a global bitline distributed to output transistors of memory cells in each of the memory banks. The output transistors are activated by a combination of a global read evaluation signal and a stored value in a corresponding one of the memory cells. The output transistors are source-coupled (their source terminals coupled) to either the global read evaluation signal or the stored value in the corresponding one of the memory cells. Herein the global read evaluation signal may be referred to as rcselb and the signal representing the stored value in a memory cell may be referred to as rnand_out.

The source-coupling to either the global read evaluation signal or the stored value in the corresponding one of the memory cells may be achieved via an inverter. The circuit may comprise two or more of the output transistors source-coupled to the global read evaluation signal via a shared inverter.

The circuit embodiments may be implemented as a plurality of bit-storing cells each comprising an output transistor. The output transistors form an NOR gate distributed across the bit-storing cells. The circuit includes logic (e.g., in the form of transistor circuit structure) to sustain a high binary voltage level on an output of the NOR gate, on condition that a read signal is applied to the plurality of bit-storing cells and also that a value stored in an evaluated bit-storing cell satisfies a value (e.g., is a “1”). A stored value is said to “satisfy” a value when it has that value or corresponds to common logical interpretation with the value. For example, a stored value may satisfy a high binary voltage level if both correspond to an interpretation of logical “1”. Because bit-storing cells often store both a value and the complement of the value, the “stored value” should be understood to exclude the complement value, unless otherwise indicated.

To sustain the high binary voltage level on the output of the NOR gate, the read signal (e.g., a read evaluation signal in an SRAM) may be applied to source terminals of one or more output transistors of the bit-storing cell.

The circuit may also sustain the high binary voltage level on the output of the NOR gate by applying the values stored in particular ones of the bit-storing cells to source terminals of the corresponding output transistors of the particular bit-storing cells.

The circuit may also sustain the high binary voltage level on the output of the NOR gate by applying the read signal to a first pull-up transistor on drain terminals of one or more output transistors of the bit-storing cell, and further applying the values stored in bit-storing cell corresponding to the output transistor to a second pull-up transistor on the drain of the output transistor.

In one specific aspect, a static random access memory (SRAM) may include a plurality of memory banks each including memory cells, and a hierarchical bitline structure that includes local bitlines for the memory banks and a global bitline spanning the memory banks. A keeper circuit for the global bitline may be replaced by bias circuitry on output transistors of the memory cells.

The bias circuitry may in some embodiments apply a global read evaluation signal as a source bias on the output transistors. The bias circuitry may alternatively be configured to apply a stored bit value from the memory cell as a source bias on a corresponding output transistor.

The SRAM may in some embodiments apply (a) a global read evaluation signal and (b) a stored bit value from a memory cell to generate a source bias on a corresponding output transistor.

In another aspect, a machine memory system includes a plurality of bit-storing cells, a memory controller, and a global bitline coupling the memory controller to the plurality of bit-storing cells. A distributed NOR gate is configured as an input to the global bitline from the plurality of bit-storing cells, with logic to sustain a high binary voltage level output from the distributed NOR gate onto the global bitline in response to (a) a read signal applied by the memory controller to the bit-storing cell, and (b) stored bit values from the bit-storing cells.

The high binary voltage level may be sustained by logic to apply the read signal to source terminals of output transistors of the bit-storing cells, or by logic to apply the stored bit values to source terminals of output transistors of the bit-storing cells, or by logic to apply the read signal to first pull-up transistors on drain terminals of output transistors of the bit-storing cells, and to apply the stored bit values to second pull-up transistors on drain terminals of the output transistors.

Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.

FIG. 1 depicts memory cells 100 in a machine memory circuit in one embodiment. The memory cells 100 may utilize a six- or eight- transistor technology, for example. Vertical lines represent bitlines 102 and horizontal lines represent word lines 104. In this example the word line WL(n-1) is selected, meaning activated to perform a memory operation on one of the cells along the word line. The bitlines for full-selected cell 106 are also activated, and in conjunction with assertion of the word line WL(n-1) fully selects the full-selected cell 106 for a memory operation. The bitlines for the half-selected cells 108 are not activated, hence the cells are “half-selected”.

FIG. 2 depicts a memory controller 202 in one embodiment. A row address decoder 204 translates a memory address into a row (word line) selection, and a column decoder 206 translates the address into column (bitline) selection(s). The bit-storing cells along the selected row and column are read by the column multiplexer 208, which includes latches for data read from the machine memory 210, keeper logic (described below), and logic for writing values into the bit-storing cells of the machine memory 210. These operations may be performed synchronously and thus coordinated by a clock 212.

FIG. 3 depicts an example of (two) bit-storing cells and associated logic to read the values stored in the cells out to a global bitline (grblb). FIG. 4 depicts another example of (two) bit-storing cells and associated logic to read the values stored in the cells out to the global bitline grblb.

FIG. 5 depicts logic to read the values stored in a number of bit-storing cells as organized along a global bitline 502 (grblb). Leakage occurs through the output transistors 504 of unselected bit-storing cells and this may cause discharge of the global bitline 502 from its precharged high binary voltage level. While not a problem during read evaluation 1 operations, this may lead to erroneous readings during read evaluation 0 operations.

Referring to FIG. 6 , during read evaluation 1, signal rblb_s is not discharged through the bitcell being evaluated, and rblb_n discharge through bitcell which cause Signal rnand_out is thus set high and pulls grblb toward ground plane voltage VSS. During read evaluation 0, rblb_s does not discharge through the bitcell and retains its precharge voltage, rblb_n also retains its precharge voltage, and grblb stays, in theory, at VDD because no discharge occurs through any local output transistor of the bit-storing cells on grblb (they all stay “off”). However in practice, leakage occurs through the many “off” output transistors of the other bit-storing cells along grblb. Because read evaluation 0 takes a relatively long time to complete to the point of stable sensing, the leakage may pull the voltage on grblb below the point where the sensing circuit detects a low binary voltage level instead of high binary voltage level on grblb.

Evaluation 1 refers to a process whereby a stored “1” causes the discharging of grblb, and evaluation 0 refers to a process whereby a stored “0” causes grblb to remain in a precharged state. FIG. 7 depicts read evaluation 1 signal timing in one embodiment. When the selected bit-storing cell stores a “1”, rnand_out quickly pulls grblb to “0” and the stored “1” is sensed with adequate timing margin.

FIG. 8 depicts read evaluation 0 signal timing in one embodiment. When the selected bit-storing cell stores a “0”, rnand_out remains at VSS and grblb (ideally) remains at the precharged high binary voltage level (VDD) with adequate timing margin such that the “0” bit stored in the selected bit-storing cell is accurately sensed.

FIG. 9 depicts a timing diagram for read evaluation 1 and read evaluation 0 with respect to grblb keeper signal. For read evaluation 1, the keeper signal is triggered soon after the discharge of grblb, so as not to interfere with the discharge and create an erroneous reading. During read evaluation 0 grblb should ideally remain charged to VDD but due to leakage it may discharge to the point that an erroneous “1” value is detected in the evaluated cell. If the keeper signal is not triggered, grblb will start to discharge due to leakage (as depicted), which may, depending on latencies in the system, lead to erroneous readings. Hence the timing of the grblb keeper signal is critical. Because leakage and other factors may vary over large circuit areas due to process, timing, and voltage variations, among other things, the timing of the keeper signal becomes highly constrained.

FIG. 10 depicts a global bitline precharge driver 1002 and keeper circuit 1004 in one embodiment.

In a precharge phase, signal grblb_pc is activated (e.g., active “low”) to pull the global bitline grblb “high”, e.g., to a high binary voltage level VDD. Signal grblb_pc is then deactivated and the read evaluation phase begins. During this phase, a full-selected cell is evaluated for whether it stores a “0” bit or a “1” bit. These are referred to herein as “read evaluation 0” and “read evaluation 1”. The keeper circuit comes into play to prevent decay of the high binary voltage level on grblb during read evaluation 0. The transistor MP1 stays on unless/until the voltage on grblb falls sufficiently (due to leakage through other “off” output transistors on grblb) to turn it off, at which point, if rkeepb goes low before MP1 transistor turn off, grblb is pulled back up to the high binary voltage level and kept there sufficiently long that the sense circuity of the system detects the “0” value stored in the full-selected cell. This is referred to as “sustaining the high binary voltage level” on grblb.

If rkeepb is dropped too early during read evaluation 1, it will disturb the bit being read onto grblb which fights the discharge of grblb. If rkeepb is dropped too late, grblb may discharge too much during read evaluation 0. The precise tolerance requirements for the timing of signal rkeepb is problematic in large systems where process, voltage, and temperature variations, and/or signal propagation delays, become substantial.

FIG. 11 depicts output transistor bias circuitry in one embodiment. A dynamic source bias is conditionally applied via an inverter 1102 to the transistor that controls output to grblb of the stored bit value in the bit-storing cell. When the rcsel signal is not asserted (meaning the cell is not selected for read evaluation), the node at gnd_int is pulled high; regardless of the stored bit value in the unselected cell, this eliminates or greatly reduces leakage through the output transistor of the cell from the precharged high binary voltage level on grblb. When the rcsel signal is asserted (meaning the cell is selected for read evaluation), the node at gnd_int is pulled low; on condition that the stored bit value is “0” in the selected cell, rnand_out turns off the output transistor, and the high binary voltage level on grblb from precharge is sustained (with perhaps minor leakage through the single output transistor of the selected bit-storing cell).

The dynamic source bias on the output transistor thus replaces the conventional keeper circuit and obviates the timing constraints associated therewith. FIG. 12 depicts an exemplary timing diagram for read evaluation 1 in this scenario, and FIG. 13 exemplifies the discharge of grblb when the selected cell evaluates to 1. FIG. 14 depicts an exemplary timing diagram for read evaluation 0 in this scenario, and FIG. 15 exemplifies the sustained high binary voltage level on grblb when the selected cell evaluates to 0.

Although as depicted there is an inverter per output transistor, in other embodiments the circuit may comprise two or more of the output transistors source-coupled to the global read evaluation signal via a shared inverter (because rcsel is a global signal).

It may be seen from FIG. 13 that the output transistors effectively form an NOR gate distributed across the bit-storing cells. The circuit includes logic to sustain a high binary voltage level on an output of the NOR gate, on condition that a read signal is applied to the plurality of bit-storing cells and also that a value stored in an evaluated bit-storing cell satisfies a value (e.g., is a “1”).

FIG. 16 depicts output transistor bias circuitry according to another embodiment. This embodiment may achieve substantially the same functionality as the embodiment in FIG. 11 . An inverter 1602 is coupled between the rnand_out node and the source terminal of the output transistor. There is somewhat more impact on speed than in the embodiment of FIG. 11 because toggling the inverter 1602 depends on the signal values applied to rblb (local read bitline) as well as to rcselb (the selection signal for the cell to evaluate).

FIG. 17 depicts output transistor bias circuitry according to yet another embodiment. This embodiment may achieve substantially the same functionality as the embodiment in FIG. 11 . Stacked of PMOS transistors are placed on grblb with the PMOS MP0 coupled to rnand_out and MP1 coupled to rcselb. This embodiment may have less impact on area and a similar impact on speed as the embodiment in FIG. 11 .

FIG. 18 depicts output transistor bias circuitry according to yet another embodiment. This embodiment may achieve substantially the same functionality as the embodiment in FIG. 11 . This embodiment is similar to the one depicted in FIG. 17 except that the top PMOS MP0 is coupled to rcselb and MP1 is coupled to rnand_out. This embodiment may have less impact on area and a similar impact on speed as the embodiment in FIG. 11 .

The circuits disclosed herein may be executed by computing devices utilizing one or more graphic processing unit (GPU) and/or general purpose data processor (e.g., a ‘central processing unit or CPU). Exemplary architectures will now be described that may be configured with such circuits, for example for use with volatile memory devices (e.g., SRAMs).

The following description may use certain acronyms and abbreviations as follows:

-   “DPC” refers to a “data processing cluster”; -   “GPC” refers to a “general processing cluster”; -   “I/O” refers to a “input/output”; -   “L1 cache” refers to “level one cache”; -   “L2 cache” refers to “level two cache”; -   “LSU” refers to a “load/store unit”; -   “MMU” refers to a “memory management unit”; -   “MPC” refers to an “M-pipe controller”; -   “PPU” refers to a “parallel processing unit”; -   “PROP” refers to a “pre-raster operations unit”; -   “ROP” refers to a “raster operations”; -   “SFU” refers to a “special function unit”; -   “SM” refers to a “streaming multiprocessor”; -   “Viewport SCC” refers to “viewport scale, cull, and clip”; -   “WDX” refers to a “work distribution crossbar”; and -   “XBar” refers to a “crossbar”.

Parallel Processing Unit

FIG. 19 depicts a parallel processing unit 1920, in accordance with an embodiment. In an embodiment, the parallel processing unit 1920 is a multi-threaded processor that is implemented on one or more integrated circuit devices. The parallel processing unit 1920 is a latency hiding architecture designed to process many threads in parallel. A thread (e.g., a thread of execution) is an instantiation of a set of instructions configured to be executed by the parallel processing unit 1920. In an embodiment, the parallel processing unit 1920 is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data in order to generate two-dimensional (2D) image data for display on a display device such as a liquid crystal display (LCD) device. In other embodiments, the parallel processing unit 1920 may be utilized for performing general-purpose computations. While one exemplary parallel processor is provided herein for illustrative purposes, it should be strongly noted that such processor is set forth for illustrative purposes only, and that any processor may be employed to supplement and/or substitute for the same.

One or more parallel processing unit 1920 modules may be configured to accelerate thousands of High Performance Computing (HPC), data center, and machine learning applications. The parallel processing unit 1920 may be configured to accelerate numerous deep learning systems and applications including autonomous vehicle platforms, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and the like.

As shown in FIG. 19 , the parallel processing unit 1920 includes an I/O unit 1902, a front-end unit 1904, a scheduler unit 1908, a work distribution unit 1910, a hub 1906, a crossbar 1914, one or more general processing cluster 2000 modules, and one or more memory partition unit 2100 modules. The parallel processing unit 1920 may be connected to a host processor or other parallel processing unit 1920 modules via one or more high-speed NVLink 1916 interconnects. The parallel processing unit 1920 may be connected to a host processor or other peripheral devices via an interconnect 1918. The parallel processing unit 1920 may also be connected to a local memory comprising a number of memory 1912 devices. In an embodiment, the local memory may comprise a number of dynamic random access memory (DRAM) devices. The DRAM devices may be configured as a high-bandwidth memory (HBM) subsystem, with multiple DRAM dies stacked within each device. The memory 1912 may comprise logic to configure the parallel processing unit 1920 to carry out aspects of the techniques disclosed herein.

The NVLink 1916 interconnect enables systems to scale and include one or more parallel processing unit 1920 modules combined with one or more CPUs, supports cache coherence between the parallel processing unit 1920 modules and CPUs, and CPU mastering. Data and/or commands may be transmitted by the NVLink 1916 through the hub 1906 to/from other units of the parallel processing unit 1920 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). The NVLink 1916 is described in more detail in conjunction with FIG. 23 .

The I/O unit 1902 is configured to transmit and receive communications (e.g., commands, data, etc.) from a host processor (not shown) over the interconnect 1918. The I/O unit 1902 may communicate with the host processor directly via the interconnect 1918 or through one or more intermediate devices such as a memory bridge. In an embodiment, the I/O unit 1902 may communicate with one or more other processors, such as one or more parallel processing unit 1920 modules via the interconnect 1918. In an embodiment, the I/O unit 1902 implements a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus and the interconnect 1918 is a PCIe bus. In alternative embodiments, the I/O unit 1902 may implement other types of well-known interfaces for communicating with external devices.

The I/O unit 1902 decodes packets received via the interconnect 1918. In an embodiment, the packets represent commands configured to cause the parallel processing unit 1920 to perform various operations. The I/O unit 1902 transmits the decoded commands to various other units of the parallel processing unit 1920 as the commands may specify. For example, some commands may be transmitted to the front-end unit 1904. Other commands may be transmitted to the hub 1906 or other units of the parallel processing unit 1920 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the I/O unit 1902 is configured to route communications between and among the various logical units of the parallel processing unit 1920.

In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the parallel processing unit 1920 for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (e.g., read/write) by both the host processor and the parallel processing unit 1920. For example, the I/O unit 1902 may be configured to access the buffer in a system memory connected to the interconnect 1918 via memory requests transmitted over the interconnect 1918. In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the parallel processing unit 1920. The front-end unit 1904 receives pointers to one or more command streams. The front-end unit 1904 manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the parallel processing unit 1920.

The front-end unit 1904 is coupled to a scheduler unit 1908 that configures the various general processing cluster 2000 modules to process tasks defined by the one or more streams. The scheduler unit 1908 is configured to track state information related to the various tasks managed by the scheduler unit 1908. The state may indicate which general processing cluster 2000 a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler unit 1908 manages the execution of a plurality of tasks on the one or more general processing cluster 2000 modules.

The scheduler unit 1908 is coupled to a work distribution unit 1910 that is configured to dispatch tasks for execution on the general processing cluster 2000 modules. The work distribution unit 1910 may track a number of scheduled tasks received from the scheduler unit 1908. In an embodiment, the work distribution unit 1910 manages a pending task pool and an active task pool for each of the general processing cluster 2000 modules. The pending task pool may comprise a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular general processing cluster 2000. The active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by the general processing cluster 2000 modules. As a general processing cluster 2000 finishes the execution of a task, that task is evicted from the active task pool for the general processing cluster 2000 and one of the other tasks from the pending task pool is selected and scheduled for execution on the general processing cluster 2000. If an active task has been idle on the general processing cluster 2000, such as while waiting for a data dependency to be resolved, then the active task may be evicted from the general processing cluster 2000 and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the general processing cluster 2000.

The work distribution unit 1910 communicates with the one or more general processing cluster 2000 modules via crossbar 1914. The crossbar 1914 is an interconnect network that couples many of the units of the parallel processing unit 1920 to other units of the parallel processing unit 1920. For example, the crossbar 1914 may be configured to couple the work distribution unit 1910 to a particular general processing cluster 2000. Although not shown explicitly, one or more other units of the parallel processing unit 1920 may also be connected to the crossbar 1914 via the hub 1906.

The tasks are managed by the scheduler unit 1908 and dispatched to a general processing cluster 2000 by the work distribution unit 1910. The general processing cluster 2000 is configured to process the task and generate results. The results may be consumed by other tasks within the general processing cluster 2000, routed to a different general processing cluster 2000 via the crossbar 1914, or stored in the memory 1912. The results can be written to the memory 1912 via the memory partition unit 2100 modules, which implement a memory interface for reading and writing data to/from the memory 1912. The results can be transmitted to another parallel processing unit 1920 or CPU via the NVLink 1916. In an embodiment, the parallel processing unit 1920 includes a number U of memory partition unit 2100 modules that is equal to the number of separate and distinct memory 1912 devices coupled to the parallel processing unit 1920. A memory partition unit 2100 will be described in more detail below in conjunction with FIG. 21 .

In an embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the parallel processing unit 1920. In an embodiment, multiple compute applications are simultaneously executed by the parallel processing unit 1920 and the parallel processing unit 1920 provides isolation, quality of service (QoS), and independent address spaces for the multiple compute applications. An application may generate instructions (e.g., API calls) that cause the driver kernel to generate one or more tasks for execution by the parallel processing unit 1920. The driver kernel outputs tasks to one or more streams being processed by the parallel processing unit 1920. Each task may comprise one or more groups of related threads, referred to herein as a warp. In an embodiment, a warp comprises 32 related threads that may be executed in parallel. Cooperating threads may refer to a plurality of threads including instructions to perform the task and that may exchange data through shared memory. Threads and cooperating threads are described in more detail in conjunction with FIG. 22 .

FIG. 20 depicts a general processing cluster 2000 of the parallel processing unit 1920 of FIG. 19 , in accordance with an embodiment. As shown in FIG. 20 , each general processing cluster 2000 includes a number of hardware units for processing tasks. In an embodiment, each general processing cluster 2000 includes a pipeline manager 2002, a pre-raster operations unit 2004, a raster engine 2008, a work distribution crossbar 2014, a memory management unit 2016, and one or more data processing cluster 2006. It will be appreciated that the general processing cluster 2000 of FIG. 20 may include other hardware units in lieu of or in addition to the units shown in FIG. 20 .

In an embodiment, the operation of the general processing cluster 2000 is controlled by the pipeline manager 2002. The pipeline manager 2002 manages the configuration of the one or more data processing cluster 2006 modules for processing tasks allocated to the general processing cluster 2000. In an embodiment, the pipeline manager 2002 may configure at least one of the one or more data processing cluster 2006 modules to implement at least a portion of a graphics rendering pipeline. For example, a data processing cluster 2006 may be configured to execute a vertex shader program on the programmable streaming multiprocessor 2200. The pipeline manager 2002 may also be configured to route packets received from the work distribution unit 1910 to the appropriate logical units within the general processing cluster 2000. For example, some packets may be routed to fixed function hardware units in the pre-raster operations unit 2004 and/or raster engine 2008 while other packets may be routed to the data processing cluster 2006 modules for processing by the primitive engine 2012 or the streaming multiprocessor 2200. In an embodiment, the pipeline manager 2002 may configure at least one of the one or more data processing cluster 2006 modules to implement a neural network model and/or a computing pipeline.

The pre-raster operations unit 2004 is configured to route data generated by the raster engine 2008 and the data processing cluster 2006 modules to a Raster Operations (ROP) unit, described in more detail in conjunction with FIG. 21 . The pre-raster operations unit 2004 may also be configured to perform optimizations for color blending, organize pixel data, perform address translations, and the like.

The raster engine 2008 includes a number of fixed function hardware units configured to perform various raster operations. In an embodiment, the raster engine 2008 includes a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, and a tile coalescing engine. The setup engine receives transformed vertices and generates plane equations associated with the geometric primitive defined by the vertices. The plane equations are transmitted to the coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for the primitive. The output of the coarse raster engine is transmitted to the culling engine where fragments associated with the primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. Those fragments that survive clipping and culling may be passed to the fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. The output of the raster engine 2008 comprises fragments to be processed, for example, by a fragment shader implemented within a data processing cluster 2006.

Each data processing cluster 2006 included in the general processing cluster 2000 includes an M-pipe controller 2010, a primitive engine 2012, and one or more streaming multiprocessor 2200 modules. The M-pipe controller 2010 controls the operation of the data processing cluster 2006, routing packets received from the pipeline manager 2002 to the appropriate units in the data processing cluster 2006. For example, packets associated with a vertex may be routed to the primitive engine 2012, which is configured to fetch vertex attributes associated with the vertex from the memory 1912. In contrast, packets associated with a shader program may be transmitted to the streaming multiprocessor 2200.

The streaming multiprocessor 2200 comprises a programmable streaming processor that is configured to process tasks represented by a number of threads. Each streaming multiprocessor 2200 is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently. In an embodiment, the streaming multiprocessor 2200 implements a Single-Instruction, Multiple-Data (SIMD) architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. All threads in the group of threads execute the same instructions. In another embodiment, the streaming multiprocessor 2200 implements a Single-Instruction, Multiple Thread (SIMT) architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution. In an embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. When execution state is maintained for each individual thread, threads executing the same instructions may be converged and executed in parallel for maximum efficiency. The streaming multiprocessor 2200 will be described in more detail below in conjunction with FIG. 22 .

The memory management unit 2016 provides an interface between the general processing cluster 2000 and the memory partition unit 2100. The memory management unit 2016 may provide translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In an embodiment, the memory management unit 2016 provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in the memory 1912.

FIG. 21 depicts a memory partition unit 2100 of the parallel processing unit 1920 of FIG. 19 , in accordance with an embodiment. As shown in FIG. 21 , the memory partition unit 2100 includes a raster operations unit 2102, a level two cache 2104, and a memory interface 2106. The memory interface 2106 is coupled to the memory 1912. Memory interface 2106 may implement 32, 64, 128, 1024-bit data buses, or the like, for high-speed data transfer. In an embodiment, the parallel processing unit 1920 incorporates U memory interface 2106 modules, one memory interface 2106 per pair of memory partition unit 2100 modules, where each pair of memory partition unit 2100 modules is connected to a corresponding memory 1912 device. For example, parallel processing unit 1920 may be connected to up to Y memory 1912 devices, such as high bandwidth memory stacks or graphics double-data-rate, version 5, synchronous dynamic random access memory, or other types of persistent storage.

In an embodiment, the memory interface 2106 implements an HBM2 memory interface and Y equals half U. In an embodiment, the HBM2 memory stacks are located on the same physical package as the parallel processing unit 1920, providing substantial power and area savings compared with conventional GDDR5 SDRAM systems. In an embodiment, each HBM2 stack includes four memory dies and Y equals 4, with HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits.

In an embodiment, the memory 1912 supports Single-Error Correcting Double-Error Detecting (SECDED) Error Correction Code (ECC) to protect data. ECC provides higher reliability for compute applications that are sensitive to data corruption. Reliability is especially important in large-scale cluster computing environments where parallel processing unit 1920 modules process very large datasets and/or run applications for extended periods.

In an embodiment, the parallel processing unit 1920 implements a multi-level memory hierarchy. In an embodiment, the memory partition unit 2100 supports a unified memory to provide a single unified virtual address space for CPU and parallel processing unit 1920 memory, enabling data sharing between virtual memory systems. In an embodiment the frequency of accesses by a parallel processing unit 1920 to memory located on other processors is traced to ensure that memory pages are moved to the physical memory of the parallel processing unit 1920 that is accessing the pages more frequently. In an embodiment, the NVLink 1916 supports address translation services allowing the parallel processing unit 1920 to directly access a CPU’s page tables and providing full access to CPU memory by the parallel processing unit 1920.

In an embodiment, copy engines transfer data between multiple parallel processing unit 1920 modules or between parallel processing unit 1920 modules and CPUs. The copy engines can generate page faults for addresses that are not mapped into the page tables. The memory partition unit 2100 can then service the page faults, mapping the addresses into the page table, after which the copy engine can perform the transfer. In a conventional system, memory is pinned (e.g., non-pageable) for multiple copy engine operations between multiple processors, substantially reducing the available memory. With hardware page faulting, addresses can be passed to the copy engines without worrying if the memory pages are resident, and the copy process is transparent.

Data from the memory 1912 or other system memory may be fetched by the memory partition unit 2100 and stored in the level two cache 2104, which is located on-chip and is shared between the various general processing cluster 2000 modules. As shown, each memory partition unit 2100 includes a portion of the level two cache 2104 associated with a corresponding memory 1912 device. Lower level caches may then be implemented in various units within the general processing cluster 2000 modules. For example, each of the streaming multiprocessor 2200 modules may implement an L1 cache. The L1 cache is private memory that is dedicated to a particular streaming multiprocessor 2200. Data from the level two cache 2104 may be fetched and stored in each of the L1 caches for processing in the functional units of the streaming multiprocessor 2200 modules. The level two cache 2104 is coupled to the memory interface 2106 and the crossbar 1914.

The raster operations unit 2102 performs graphics raster operations related to pixel color, such as color compression, pixel blending, and the like. The raster operations unit 2102 also implements depth testing in conjunction with the raster engine 2008, receiving a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine 2008. The depth is tested against a corresponding depth in a depth buffer for a sample location associated with the fragment. If the fragment passes the depth test for the sample location, then the raster operations unit 2102 updates the depth buffer and transmits a result of the depth test to the raster engine 2008. It will be appreciated that the number of partition memory partition unit 2100 modules may be different than the number of general processing cluster 2000 modules and, therefore, each raster operations unit 2102 may be coupled to each of the general processing cluster 2000 modules. The raster operations unit 2102 tracks packets received from the different general processing cluster 2000 modules and determines which general processing cluster 2000 that a result generated by the raster operations unit 2102 is routed to through the crossbar 1914. Although the raster operations unit 2102 is included within the memory partition unit 2100 in FIG. 21 , in other embodiment, the raster operations unit 2102 may be outside of the memory partition unit 2100. For example, the raster operations unit 2102 may reside in the general processing cluster 2000 or another unit.

FIG. 22 illustrates the streaming multiprocessor 2200 of FIG. 20 , in accordance with an embodiment. As shown in FIG. 22 , the streaming multiprocessor 2200 includes an instruction cache 2202, one or more scheduler unit 2204 modules (e.g., such as scheduler unit 1908), a register file 2208, one or more processing core 2210 modules, one or more special function unit 2212 modules, one or more load/store unit 2214 modules, an interconnect network 2216, and a shared memory/L1 cache 2218.

As described above, the work distribution unit 1910 dispatches tasks for execution on the general processing cluster 2000 modules of the parallel processing unit 1920. The tasks are allocated to a particular data processing cluster 2006 within a general processing cluster 2000 and, if the task is associated with a shader program, the task may be allocated to a streaming multiprocessor 2200. The scheduler unit 1908 receives the tasks from the work distribution unit 1910 and manages instruction scheduling for one or more thread blocks assigned to the streaming multiprocessor 2200. The scheduler unit 2204 schedules thread blocks for execution as warps of parallel threads, where each thread block is allocated at least one warp. In an embodiment, each warp executes 32 threads. The scheduler unit 2204 may manage a plurality of different thread blocks, allocating the warps to the different thread blocks and then dispatching instructions from the plurality of different cooperative groups to the various functional units (e.g., core 2210 modules, special function unit 2212 modules, and load/store unit 2214 modules) during each clock cycle.

Cooperative Groups is a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, enabling the expression of richer, more efficient parallel decompositions. Cooperative launch APIs support synchronization amongst thread blocks for the execution of parallel algorithms. Conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads( ) function). However, programmers would often like to define groups of threads at smaller than thread block granularities and synchronize within the defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces.

Cooperative Groups enables programmers to define groups of threads explicitly at sub-block (e.g., as small as a single thread) and multi-block granularities, and to perform collective operations such as synchronization on the threads in a cooperative group. The programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. Cooperative Groups primitives enable new patterns of cooperative parallelism, including producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

A dispatch 2206 unit is configured within the scheduler unit 2204 to transmit instructions to one or more of the functional units. In one embodiment, the scheduler unit 2204 includes two dispatch 2206 units that enable two different instructions from the same warp to be dispatched during each clock cycle. In alternative embodiments, each scheduler unit 2204 may include a single dispatch 2206 unit or additional dispatch 2206 units.

Each streaming multiprocessor 2200 includes a register file 2208 that provides a set of registers for the functional units of the streaming multiprocessor 2200. In an embodiment, the register file 2208 is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file 2208. In another embodiment, the register file 2208 is divided between the different warps being executed by the streaming multiprocessor 2200. The register file 2208 provides temporary storage for operands connected to the data paths of the functional units.

Each streaming multiprocessor 2200 comprises L processing core 2210 modules. In an embodiment, the streaming multiprocessor 2200 includes a large number (e.g., 128, etc.) of distinct processing core 2210 modules. Each core 2210 may include a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit. In an embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. In an embodiment, the core 2210 modules include 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

Tensor cores configured to perform matrix operations, and, in an embodiment, one or more tensor cores are included in the core 2210 modules. In particular, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In an embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A′B+C, where A, B, C, and D are 4×4 matrices.

In an embodiment, the matrix multiply inputs A and B are 16-bit floating point matrices, while the accumulation matrices C and D may be 16-bit floating point or 32-bit floating point matrices. Tensor Cores operate on 16-bit floating point input data with 32-bit floating point accumulation. The 16-bit floating point multiply requires 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with the other intermediate products for a 4×4×4 matrix multiply. In practice, Tensor Cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements. An API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use Tensor Cores from a CUDA-C++ program. At the CUDA level, the warp-level interface assumes 16×16 size matrices spanning all 32 threads of the warp.

Each streaming multiprocessor 2200 also comprises M special function unit 2212 modules that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like). In an embodiment, the special function unit 2212 modules may include a tree traversal unit configured to traverse a hierarchical tree data structure. In an embodiment, the special function unit 2212 modules may include texture unit configured to perform texture map filtering operations. In an embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texels) from the memory 1912 and sample the texture maps to produce sampled texture values for use in shader programs executed by the streaming multiprocessor 2200. In an embodiment, the texture maps are stored in the shared memory/L1 cache 2218. The texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail). In an embodiment, each streaming multiprocessor 2200 includes two texture units.

Each streaming multiprocessor 2200 also comprises N load/store unit 2214 modules that implement load and store operations between the shared memory/L1 cache 2218 and the register file 2208. Each streaming multiprocessor 2200 includes an interconnect network 2216 that connects each of the functional units to the register file 2208 and the load/store unit 2214 to the register file 2208 and shared memory/L1 cache 2218. In an embodiment, the interconnect network 2216 is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file 2208 and connect the load/store unit 2214 modules to the register file 2208 and memory locations in shared memory/L1 cache 2218.

The shared memory/L1 cache 2218 is an array of on-chip memory that allows for data storage and communication between the streaming multiprocessor 2200 and the primitive engine 2012 and between threads in the streaming multiprocessor 2200. In an embodiment, the shared memory/L1 cache 2218 comprises 128 KB of storage capacity and is in the path from the streaming multiprocessor 2200 to the memory partition unit 2100. The shared memory/L1 cache 2218 can be used to cache reads and writes. One or more of the shared memory/L1 cache 2218, level two cache 2104, and memory 1912 are backing stores.

Combining data cache and shared memory functionality into a single memory block provides the best overall performance for both types of memory accesses. The capacity is usable as a cache by programs that do not use shared memory. For example, if shared memory is configured to use half of the capacity, texture and load/store operations can use the remaining capacity. Integration within the shared memory/L1 cache 2218 enables the shared memory/L1 cache 2218 to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data.

When configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. Specifically, the fixed function graphics processing units shown in FIG. 19 , are bypassed, creating a much simpler programming model. In the general purpose parallel computation configuration, the work distribution unit 1910 assigns and distributes blocks of threads directly to the data processing cluster 2006 modules. The threads in a block execute the same program, using a unique thread ID in the calculation to ensure each thread generates unique results, using the streaming multiprocessor 2200 to execute the program and perform calculations, shared memory/L1 cache 2218 to communicate between threads, and the load/store unit 2214 to read and write global memory through the shared memory/L1 cache 2218 and the memory partition unit 2100. When configured for general purpose parallel computation, the streaming multiprocessor 2200 can also write commands that the scheduler unit 1908 can use to launch new work on the data processing cluster 2006 modules.

The parallel processing unit 1920 may be included in a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and the like. In an embodiment, the parallel processing unit 1920 is embodied on a single semiconductor substrate. In another embodiment, the parallel processing unit 1920 is included in a system-on-a-chip (SoC) along with one or more other devices such as additional parallel processing unit 1920 modules, the memory 1912, a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like.

In an embodiment, the parallel processing unit 1920 may be included on a graphics card that includes one or more memory devices. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the parallel processing unit 1920 may be an integrated graphics processing unit (iGPU) or parallel processor included in the chipset of the motherboard.

Exemplary Computing System

Systems with multiple GPUs and CPUs are used in a variety of industries as developers expose and leverage more parallelism in applications such as artificial intelligence computing. High-performance GPU-accelerated systems with tens to many thousands of compute nodes are deployed in data centers, research facilities, and supercomputers to solve ever larger problems. As the number of processing devices within the high-performance systems increases, the communication and data transfer mechanisms need to scale to support the increased bandwidth.

FIG. 23 is a conceptual diagram of a processing system 2300 implemented using the parallel processing unit 1920 of FIG. 19 , in accordance with an embodiment. The processing system 2300 includes a central processing unit 2306, switch 2304, and multiple parallel processing unit 1920 modules each and respective memory 1912 modules. The NVLink 1916 provides high-speed communication links between each of the parallel processing unit 1920 modules. Although a particular number of NVLink 1916 and interconnect 1918 connections are illustrated in FIG. 23 , the number of connections to each parallel processing unit 1920 and the central processing unit 2306 may vary. The switch 2304 interfaces between the interconnect 1918 and the central processing unit 2306. The parallel processing unit 1920 modules, memory 1912 modules, and NVLink 1916 connections may be situated on a single semiconductor platform to form a parallel processing module 2302. In an embodiment, the switch 2304 supports two or more protocols to interface between various different connections and/or links.

In another embodiment (not shown), the NVLink 1916 provides one or more high-speed communication links between each of the parallel processing unit modules (parallel processing unit 1920, parallel processing unit 1920, parallel processing unit 1920, and parallel processing unit 1920) and the central processing unit 2306 and the switch 2304 interfaces between the interconnect 1918 and each of the parallel processing unit modules. The parallel processing unit modules, memory 1912 modules, and interconnect 1918 may be situated on a single semiconductor platform to form a parallel processing module 2302. In yet another embodiment (not shown), the interconnect 1918 provides one or more communication links between each of the parallel processing unit modules and the central processing unit 2306 and the switch 2304 interfaces between each of the parallel processing unit modules using the NVLink 1916 to provide one or more high-speed communication links between the parallel processing unit modules. In another embodiment (not shown), the NVLink 1916 provides one or more high-speed communication links between the parallel processing unit modules and the central processing unit 2306 through the switch 2304. In yet another embodiment (not shown), the interconnect 1918 provides one or more communication links between each of the parallel processing unit modules directly. One or more of the NVLink 1916 high-speed communication links may be implemented as a physical NVLink interconnect or either an on-chip or on-die interconnect using the same protocol as the NVLink 1916.

In the context of the present description, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit fabricated on a die or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation and make substantial improvements over utilizing a conventional bus implementation. Of course, the various circuits or devices may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. Alternately, the parallel processing module 2302 may be implemented as a circuit board substrate and each of the parallel processing unit modules and/or memory 1912 modules may be packaged devices. In an embodiment, the central processing unit 2306, switch 2304, and the parallel processing module 2302 are situated on a single semiconductor platform.

In an embodiment, the signaling rate of each NVLink 1916 is 20 to 25 Gigabits/second and each parallel processing unit module includes six NVLink 1916 interfaces (as shown in FIG. 23 , five NVLink 1916 interfaces are included for each parallel processing unit module). Each NVLink 1916 provides a data transfer rate of 25 Gigabytes/second in each direction, with six links providing 300 Gigabytes/second. The NVLink 1916 can be used exclusively for PPU-to-PPU communication as shown in FIG. 23 , or some combination of PPU-to-PPU and PPU-to-CPU, when the central processing unit 2306 also includes one or more NVLink 1916 interfaces.

In an embodiment, the NVLink 1916 allows direct load/store/atomic access from the central processing unit 2306 to each parallel processing unit module’s memory 1912. In an embodiment, the NVLink 1916 supports coherency operations, allowing data read from the memory 1912 modules to be stored in the cache hierarchy of the central processing unit 2306, reducing cache access latency for the central processing unit 2306. In an embodiment, the NVLink 1916 includes support for Address Translation Services (ATS), enabling the parallel processing unit module to directly access page tables within the central processing unit 2306. One or more of the NVLink 1916 may also be configured to operate in a low-power mode.

FIG. 24 depicts an exemplary processing system 2400 in which the various architecture and/or functionality of the various previous embodiments may be implemented. As shown, an exemplary processing system 2400 is provided including at least one central processing unit 2306 that is connected to a communications bus 2410. The communication communications bus 2410 may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). The exemplary processing system 2400 also includes a main memory 2402. Control logic (software) and data are stored in the main memory 2402 which may take the form of random access memory (RAM).

The exemplary processing system 2400 also includes input devices 2408, the parallel processing module 2302, and display devices 2406, e.g. a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display or the like. User input may be received from the input devices 2408, e.g., keyboard, mouse, touchpad, microphone, and the like. Each of the foregoing modules and/or devices may even be situated on a single semiconductor platform to form the exemplary processing system 2400. Alternately, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user.

Further, the exemplary processing system 2400 may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) through a network interface 2404 for communication purposes.

The exemplary processing system 2400 may also include a secondary storage (not shown). The secondary storage includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (DVD) drive, recording device, universal serial bus (USB) flash memory. The removable storage drive reads from and/or writes to a removable storage unit in a well-known manner.

Computer programs, or computer control logic algorithms, may be stored in the main memory 2402 and/or the secondary storage. Such computer programs, when executed, enable the exemplary processing system 2400 to perform various functions. The main memory 2402, the storage, and/or any other storage are possible examples of computer-readable media.

The architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the exemplary processing system 2400 may take the form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic.

While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Graphics Processing Pipeline

FIG. 25 is a conceptual diagram of a graphics processing pipeline 2500 implemented by the parallel processing unit 1920 of FIG. 19 , in accordance with an embodiment. In an embodiment, the parallel processing unit 1920 comprises a graphics processing unit (GPU). The parallel processing unit 1920 is configured to receive commands that specify shader programs for processing graphics data. Graphics data may be defined as a set of primitives such as points, lines, triangles, quads, triangle strips, and the like. Typically, a primitive includes data that specifies a number of vertices for the primitive (e.g., in a model-space coordinate system) as well as attributes associated with each vertex of the primitive. The parallel processing unit 1920 can be configured to process the graphics primitives to generate a frame buffer (e.g., pixel data for each of the pixels of the display).

An application writes model data for a scene (e.g., a collection of vertices and attributes) to a memory such as a system memory or memory 1912. The model data defines each of the objects that may be visible on a display. The application then makes an API call to the driver kernel that requests the model data to be rendered and displayed. The driver kernel reads the model data and writes commands to the one or more streams to perform operations to process the model data. The commands may reference different shader programs to be implemented on the streaming multiprocessor 2200 modules of the parallel processing unit 1920 including one or more of a vertex shader, hull shader, domain shader, geometry shader, and a pixel shader. For example, one or more of the streaming multiprocessor 2200 modules may be configured to execute a vertex shader program that processes a number of vertices defined by the model data. In an embodiment, the different streaming multiprocessor 2200 modules may be configured to execute different shader programs concurrently. For example, a first subset of streaming multiprocessor 2200 modules may be configured to execute a vertex shader program while a second subset of streaming multiprocessor 2200 modules may be configured to execute a pixel shader program. The first subset of streaming multiprocessor 2200 modules processes vertex data to produce processed vertex data and writes the processed vertex data to the level two cache 2104 and/or the memory 1912. After the processed vertex data is rasterized (e.g., transformed from three-dimensional data into two-dimensional data in screen space) to produce fragment data, the second subset of streaming multiprocessor 2200 modules executes a pixel shader to produce processed fragment data, which is then blended with other processed fragment data and written to the frame buffer in memory 1912. The vertex shader program and pixel shader program may execute concurrently, processing different data from the same scene in a pipelined fashion until all of the model data for the scene has been rendered to the frame buffer. Then, the contents of the frame buffer are transmitted to a display controller for display on a display device.

The graphics processing pipeline 2500 is an abstract flow diagram of the processing steps implemented to generate 2D computer-generated images from 3D geometry data. As is well-known, pipeline architectures may perform long latency operations more efficiently by splitting up the operation into a plurality of stages, where the output of each stage is coupled to the input of the next successive stage. Thus, the graphics processing pipeline 2500 receives input data 601 that is transmitted from one stage to the next stage of the graphics processing pipeline 2500 to generate output data 2504. In an embodiment, the graphics processing pipeline 2500 may represent a graphics processing pipeline defined by the OpenGL® API. As an option, the graphics processing pipeline 2500 may be implemented in the context of the functionality and architecture of the previous Figures and/or any subsequent Figure(s).

As shown in FIG. 25 , the graphics processing pipeline 2500 comprises a pipeline architecture that includes a number of stages. The stages include, but are not limited to, a data assembly 2506 stage, a vertex shading 2508 stage, a primitive assembly 2510 stage, a geometry shading 2512 stage, a viewport SCC 2514 stage, a rasterization 2516 stage, a fragment shading 2518 stage, and a raster operations 2520 stage. In an embodiment, the input data 2502 comprises commands that configure the processing units to implement the stages of the graphics processing pipeline 2500 and geometric primitives (e.g., points, lines, triangles, quads, triangle strips or fans, etc.) to be processed by the stages. The output data 2504 may comprise pixel data (e.g., color data) that is copied into a frame buffer or other type of surface data structure in a memory.

The data assembly 2506 stage receives the input data 2502 that specifies vertex data for high-order surfaces, primitives, or the like. The data assembly 2506 stage collects the vertex data in a temporary storage or queue, such as by receiving a command from the host processor that includes a pointer to a buffer in memory and reading the vertex data from the buffer. The vertex data is then transmitted to the vertex shading 2508 stage for processing.

The vertex shading 2508 stage processes vertex data by performing a set of operations (e.g., a vertex shader or a program) once for each of the vertices. Vertices may be, e.g., specified as a 4-coordinate vector (e.g., <x, y, z, w>) associated with one or more vertex attributes (e.g., color, texture coordinates, surface normal, etc.). The vertex shading 2508 stage may manipulate individual vertex attributes such as position, color, texture coordinates, and the like. In other words, the vertex shading 2508 stage performs operations on the vertex coordinates or other vertex attributes associated with a vertex. Such operations commonly including lighting operations (e.g., modifying color attributes for a vertex) and transformation operations (e.g., modifying the coordinate space for a vertex). For example, vertices may be specified using coordinates in an object-coordinate space, which are transformed by multiplying the coordinates by a matrix that translates the coordinates from the object-coordinate space into a world space or a normalized-device-coordinate (NCD) space. The vertex shading 2508 stage generates transformed vertex data that is transmitted to the primitive assembly 2510 stage.

The primitive assembly 2510 stage collects vertices output by the vertex shading 2508 stage and groups the vertices into geometric primitives for processing by the geometry shading 2512 stage. For example, the primitive assembly 2510 stage may be configured to group every three consecutive vertices as a geometric primitive (e.g., a triangle) for transmission to the geometry shading 2512 stage. In some embodiments, specific vertices may be reused for consecutive geometric primitives (e.g., two consecutive triangles in a triangle strip may share two vertices). The primitive assembly 2510 stage transmits geometric primitives (e.g., a collection of associated vertices) to the geometry shading 2512 stage.

The geometry shading 2512 stage processes geometric primitives by performing a set of operations (e.g., a geometry shader or program) on the geometric primitives. Tessellation operations may generate one or more geometric primitives from each geometric primitive. In other words, the geometry shading 2512 stage may subdivide each geometric primitive into a finer mesh of two or more geometric primitives for processing by the rest of the graphics processing pipeline 2500. The geometry shading 2512 stage transmits geometric primitives to the viewport SCC 2514 stage.

In an embodiment, the graphics processing pipeline 2500 may operate within a streaming multiprocessor and the vertex shading 2508 stage, the primitive assembly 2510 stage, the geometry shading 2512 stage, the fragment shading 2518 stage, and/or hardware/software associated therewith, may sequentially perform processing operations. Once the sequential processing operations are complete, in an embodiment, the viewport SCC 2514 stage may utilize the data. In an embodiment, primitive data processed by one or more of the stages in the graphics processing pipeline 2500 may be written to a cache (e.g. L1 cache, a vertex cache, etc.). In this case, in an embodiment, the viewport SCC 2514 stage may access the data in the cache. In an embodiment, the viewport SCC 2514 stage and the rasterization 2516 stage are implemented as fixed function circuitry.

The viewport SCC 2514 stage performs viewport scaling, culling, and clipping of the geometric primitives. Each surface being rendered to is associated with an abstract camera position. The camera position represents a location of a viewer looking at the scene and defines a viewing frustum that encloses the objects of the scene. The viewing frustum may include a viewing plane, a rear plane, and four clipping planes. Any geometric primitive entirely outside of the viewing frustum may be culled (e.g., discarded) because the geometric primitive will not contribute to the final rendered scene. Any geometric primitive that is partially inside the viewing frustum and partially outside the viewing frustum may be clipped (e.g., transformed into a new geometric primitive that is enclosed within the viewing frustum. Furthermore, geometric primitives may each be scaled based on a depth of the viewing frustum. All potentially visible geometric primitives are then transmitted to the rasterization 2516 stage.

The rasterization 2516 stage converts the 3D geometric primitives into 2D fragments (e.g. capable of being utilized for display, etc.). The rasterization 2516 stage may be configured to utilize the vertices of the geometric primitives to setup a set of plane equations from which various attributes can be interpolated. The rasterization 2516 stage may also compute a coverage mask for a plurality of pixels that indicates whether one or more sample locations for the pixel intercept the geometric primitive. In an embodiment, z-testing may also be performed to determine if the geometric primitive is occluded by other geometric primitives that have already been rasterized. The rasterization 2516 stage generates fragment data (e.g., interpolated vertex attributes associated with a particular sample location for each covered pixel) that are transmitted to the fragment shading 2518 stage.

The fragment shading 2518 stage processes fragment data by performing a set of operations (e.g., a fragment shader or a program) on each of the fragments. The fragment shading 2518 stage may generate pixel data (e.g., color values) for the fragment such as by performing lighting operations or sampling texture maps using interpolated texture coordinates for the fragment. The fragment shading 2518 stage generates pixel data that is transmitted to the raster operations 2520 stage.

The raster operations 2520 stage may perform various operations on the pixel data such as performing alpha tests, stencil tests, and blending the pixel data with other pixel data corresponding to other fragments associated with the pixel. When the raster operations 2520 stage has finished processing the pixel data (e.g., the output data 2504), the pixel data may be written to a render target such as a frame buffer, a color buffer, or the like.

It will be appreciated that one or more additional stages may be included in the graphics processing pipeline 2500 in addition to or in lieu of one or more of the stages described above. Various implementations of the abstract graphics processing pipeline may implement different stages. Furthermore, one or more of the stages described above may be excluded from the graphics processing pipeline in some embodiments (such as the geometry shading 2512 stage). Other types of graphics processing pipelines are contemplated as being within the scope of the present disclosure. Furthermore, any of the stages of the graphics processing pipeline 2500 may be implemented by one or more dedicated hardware units within a graphics processor such as parallel processing unit 1920. Other stages of the graphics processing pipeline 2500 may be implemented by programmable hardware units such as the streaming multiprocessor 2200 of the parallel processing unit 1920.

The graphics processing pipeline 2500 may be implemented via an application executed by a host processor, such as a CPU. In an embodiment, a device driver may implement an application programming interface (API) that defines various functions that can be utilized by an application in order to generate graphical data for display. The device driver is a software program that includes a plurality of instructions that control the operation of the parallel processing unit 1920. The API provides an abstraction for a programmer that lets a programmer utilize specialized graphics hardware, such as the parallel processing unit 1920, to generate the graphical data without requiring the programmer to utilize the specific instruction set for the parallel processing unit 1920. The application may include an API call that is routed to the device driver for the parallel processing unit 1920. The device driver interprets the API call and performs various operations to respond to the API call. In some instances, the device driver may perform operations by executing instructions on the CPU. In other instances, the device driver may perform operations, at least in part, by launching operations on the parallel processing unit 1920 utilizing an input/output interface between the CPU and the parallel processing unit 1920. In an embodiment, the device driver is configured to implement the graphics processing pipeline 2500 utilizing the hardware of the parallel processing unit 1920.

Various programs may be executed within the parallel processing unit 1920 in order to implement the various stages of the graphics processing pipeline 2500. For example, the device driver may launch a kernel on the parallel processing unit 1920 to perform the vertex shading 2508 stage on one streaming multiprocessor 2200 (or multiple streaming multiprocessor 2200 modules). The device driver (or the initial kernel executed by the parallel processing unit 1920) may also launch other kernels on the parallel processing unit 1920 to perform other stages of the graphics processing pipeline 2500, such as the geometry shading 2512 stage and the fragment shading 2518 stage. In addition, some of the stages of the graphics processing pipeline 2500 may be implemented on fixed unit hardware such as a rasterizer or a data assembler implemented within the parallel processing unit 1920. It will be appreciated that results from one kernel may be processed by one or more intervening fixed function hardware units before being processed by a subsequent kernel on a streaming multiprocessor 2200.

FIG. 26 depicts exemplary scenarios for use of a circuit system 2602 in accordance with some embodiments. A circuit system 2602 may be utilized in a computing system 2604, a vehicle 2606, and a robot 2608, to name just a few examples. The circuit system 2602 may comprise one or more processors and memories that utilize circuits in accordance with the embodiments described herein.

LISTING OF DRAWING ELEMENTS

-   100 memory cells -   102 bitline -   104 word line -   106 full-selected cell -   108 half-selected cell -   202 memory controller -   204 row address decoder -   206 column decoder -   208 column multiplexer -   210 machine memory -   212 clock -   502 global bitline -   504 output transistor -   1002 global bitline precharge driver -   1004 keeper circuit -   1102 inverter -   1602 inverter -   1902 I/O unit -   1904 front-end unit -   1906 hub -   1908 scheduler unit -   1910 work distribution unit -   1912 memory -   1914 crossbar -   1916 NVLink -   1918 interconnect -   1920 parallel processing unit -   2000 general processing cluster -   2002 pipeline manager -   2004 pre-raster operations unit -   2006 data processing cluster -   2008 raster engine -   2010 M-pipe controller -   2012 primitive engine -   2014 work distribution crossbar -   2016 memory management unit -   2100 memory partition unit -   2102 raster operations unit -   2104 level two cache -   2106 memory interface -   2200 streaming multiprocessor -   2202 instruction cache -   2204 scheduler unit -   2206 dispatch -   2208 register file -   2210 core -   2212 special function unit -   2214 load/store unit -   2216 interconnect network -   2218 shared memory/L1 cache -   2300 processing system -   2302 parallel processing module -   2304 switch -   2306 central processing unit -   2400 exemplary processing system -   2402 main memory -   2404 network interface -   2406 display devices -   2408 input devices -   2410 communications bus -   2500 graphics processing pipeline -   2502 input data -   2504 output data -   2506 data assembly -   2508 vertex shading -   2510 primitive assembly -   2512 geometry shading -   2514 viewport SCC -   2516 rasterization -   2518 fragment shading -   2520 raster operations -   2602 circuit system -   2604 computing system -   2606 vehicle -   2608 robot

Various functional operations described herein may be implemented in logic that is referred to using a noun or noun phrase reflecting said operation or function. For example, an association operation may be carried out by an “associator” or “correlator”. Likewise, switching may be carried out by a “switch”, selection by a “selector”, and so on. “Logic” refers to machine memory circuits and non-transitory machine readable media comprising machine-executable instructions (software and firmware), and/or circuitry (hardware) which by way of its material and/or material-energy configuration comprises control and/or procedural signals, and/or settings and values (such as resistance, impedance, capacitance, inductance, current/voltage ratings, etc.), that may be applied to influence the operation of a device. Magnetic media, electronic circuits, electrical and optical memory (both volatile and nonvolatile), and firmware are examples of logic. Logic specifically excludes pure signals or software per se (however does not exclude machine memories comprising software and thereby forming configurations of matter).

Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation-[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. A “credit distribution circuit configured to distribute credits to a plurality of processor cores” is intended to cover, for example, an integrated circuit that has circuitry that performs this function during operation, even if the integrated circuit in question is not currently being used (e.g., a power supply is not connected to it). Thus, an entity described or recited as “configured to” perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.

The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function, although it may be “configurable to” perform that function after programming.

Reciting in the appended claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Accordingly, claims in this application that do not otherwise include the “means for” [performing a function] construct should not be interpreted under 35 U.S.C § 112(f).

As used herein, the term “based on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”

As used herein, the phrase “in response to” describes one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect. That is, an effect may be solely in response to those factors, or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B.

As used herein, the terms “first,” “second,” etc. are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise. For example, in a register file having eight registers, the terms “first register” and “second register” can be used to refer to any two of the eight registers, and not, for example, just logical registers 0 and 1.

When used in the claims, the term “or” is used as an inclusive or and not as an exclusive or. For example, the phrase “at least one of x, y, or z” means any one of x, y, and z, as well as any combination thereof.

As used herein, a recitation of “and/or” with respect to two or more elements should be interpreted to mean only one element, or a combination of elements. For example, “element A, element B, and/or element C” may include only element A, only element B, only element C, element A and element B, element A and element C, element B and element C, or elements A, B, and C. In addition, “at least one of element A or element B” may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. Further, “at least one of element A and element B” may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B.

The subject matter of the present disclosure is described with specificity herein to meet statutory requirements. However, the description itself is not intended to limit the scope of this disclosure. Rather, the inventors have contemplated that the claimed subject matter might also be embodied in other ways, to include different steps or combinations of steps similar to the ones described in this document, in conjunction with other present or future technologies. Moreover, although the terms “step” and/or “block” may be used herein to connote different elements of methods employed, the terms should not be interpreted as implying any particular order among or between various steps herein disclosed unless and except when the order of individual steps is explicitly described.

Having thus described illustrative embodiments in detail, it will be apparent that modifications and variations are possible without departing from the scope of the invention as claimed. The scope of inventive subject matter is not limited to the depicted embodiments but is rather set forth in the following Claims. 

What is claimed is:
 1. A circuit comprising: a plurality of memory banks; a global bitline distributed to output transistors of memory cells in each of the memory banks; the output transistors activated by a combination of a global read evaluation signal and a stored value in a corresponding one of the memory cells; and the output transistors source-coupled to either the global read evaluation signal or the stored values in the corresponding memory cells.
 2. The circuit of claim 1, the output transistors source-coupled to the global read evaluation signal.
 3. The circuit of claim 1, the output transistors source-coupled to the stored values in the corresponding memory cells.
 4. The circuit of claim 1, the output transistors source-coupled via inverters to either the global read evaluation signal or the stored values in the corresponding memory cells.
 5. The circuit of claim 1, two or more of the output transistors source-coupled to the global read evaluation signal via a shared inverter.
 6. A circuit comprising: a plurality of bit-storing cells; a plurality of output transistors forming an NOR gate, the NOR gate comprising inputs from the plurality of bit-storing cells; and logic to sustain a high binary voltage level on an output of the NOR gate on condition that (a) a read signal is applied to the plurality of bit-storing cells, and (b) a value stored in any of the bit-storing cells satisfies the high binary voltage level.
 7. The circuit of claim 6, the logic to sustain the high binary voltage level on the output of the NOR gate comprising: logic to apply the read signal to a source of one or more output transistors of the bit-storing cells.
 8. The circuit of claim 7, the read signal applied via inverters to source terminals of the output transistors.
 9. The circuit of claim 6, the logic to sustain the high binary voltage level on the output of the NOR gate comprising: logic to apply the value stored in a particular one of the bit-storing cells to a source terminal of an output transistor of the particular one of the bit-storing cells.
 10. The circuit of claim 9, the value stored in the particular one of the bit-storing cells coupled via an inverter to the source terminal of the output transistor of the particular one of the bit-storing cells.
 11. The circuit of claim 6, the logic to sustain the high binary voltage level on the output of the NOR gate comprising: logic to apply the read signal to a gate of first pull-up transistor with a drain of first pull up transistor coupled to a drain of one or more output transistors of the bit-storing cells; and logic to apply the values stored in bit-storing cells corresponding to the output transistors to a gate of second pull-up transistor with a drain of second pull-up transistor coupled to the source of first pull up transistor.
 12. A static random access memory (SRAM) comprising: a plurality of memory banks each comprising memory cells; a hierarchical bitline structure comprising local bitlines for the memory banks and a global bitline spanning the memory banks; and wherein a keeper circuit for grblb is replaced by bias circuitry on output transistors of the memory cells.
 13. The SRAM of claim 12, the bias circuitry comprising a global read evaluation signal applied as a source bias on the output transistors.
 14. The SRAM of claim 12, the bias circuitry configured to apply a stored bit value from each of the memory cells as a source bias on a corresponding output transistor.
 15. The SRAM of claim 12, the bias circuitry comprising: logic to apply (a) a global read evaluation signal and (b) a stored bit value from each of the memory cells, to generate a source bias on corresponding ones of the output transistors.
 16. A machine memory system comprising: a plurality of bit-storing cells; a memory controller; a global bitline coupling the memory controller to the plurality of bit-storing cells; a distributed NOR gate configured as an input to grblb from the plurality of bit-storing cells; and logic to sustain a high binary voltage level output from the distributed NOR gate onto grblb in response to (a) a read signal applied by the memory controller to the bit-storing cells, and (b) a stored bit value in one of the bit-storing cells satisfying the high binary voltage level.
 17. The machine memory system of claim 16, the logic to sustain the high binary voltage level comprising: logic to apply the read signal to source terminals of output transistors of the bit-storing cells.
 18. The machine memory system of claim 17, the read signal applied via one or more inverter to the source terminals.
 19. The machine memory system of claim 16, the logic to sustain the high binary voltage level comprising: logic to apply the stored bit values to source terminals of output transistors of the bit-storing cells.
 20. The machine memory system of claim 19, the stored bit values applied via inverters to the source terminals. 